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33 mhz/32-bit pci master/target with embedded programmable logic and dual port sram ql5332 - enhanced quickpci tm device last updated 2/5/01 rev b supports all pci commands (including configuration and mwi) supports fully-customizable byte enables as a master zero-wait-state write and one-wait-state read target interface supports all types of pci target terminations: disconnect with data transfer, disconnect without data transfer, and retry supports target aborts has 125 more logic cells in fpga section, but 2 less ram blocks pin compatible with ql5032 high performance pci controller 32-bit / 33 mhz pci master/target zero-wait state pci master provides 132 mb/s transfer rates zero-wait-state pci target write/one-wait-state pci target read interface supports all pci commands, including configuration and mwi supports fully-customizable byte enable for master channels target interface supports retry, disconnect with/without data transfer, and target abort programmable back-end interface to optional local processor independent pci bus (33 mhz) and local bus (up to 160 mhz) clocks fully customizable pci configuration space configurable fifos with depths up to 256 reference design with driver code (win 95/98/ win 2000/nt4.0) available pci v2.2 compliant supports type 0 configuration cycles in target mode 3.3v, 5v tolerant pci signaling supports universal pci adapter designs 3.3v cmos in 208-pin pqfp and 256-pin pbga supports endian conversions unlimited/continuous burst transfers supported figure 1. ql5332 diagram extendable pci functionality support for pci host-bridge function support for configuration space from 0x40 to 0x3ff multi-function, expanded capabilities, & expansion rom capable power management, compact pci, hot-swap/ hot-plug compatible pci v2.2 power management spec compatible pci v2.2 vital product data (vpd) configuration support programmable interrupt generator i 2 o support with local processor mailbox register support programmable logic 515 logic cells 13,824 ram bits, up to 154 i/o pins 250 mhz 16-bit counters, 275 mhz datapaths, 160 mhz fifos all back-end interface and glue-logic can be implemented on chip any combination of fifos that require 12 or less quicklogic ram modules six 32-bit busses interface between the pci controller and the programmable logic ql5332 - enhanced ql5032 device highlights config space 160 mhz fifos master controller interface programmable logic 32 pci bus ? 33 mhz 32 bits (data and address) 154 user i/o pci controller dma controller high speed data path high speed logic cells target controller
2 preliminary ql5332 - quickpci tm 2 the ql5332 device in the quicklogic quickpci esp (embedded standard product) family provides a complete and customizable pci interface solution combined with programmable logic. this device eliminates any need for the designer to worry about pci bus compliance, yet allows for the maximum 32- bit pci bus bandwidth (132 mb/s). the programmable logic portion of the device contains 515 quicklogic logic cells, and 12 quicklogic dual-port ram blocks. these configurable ram blocks can be configured in many width/depth combinations. they can also be combined with logic cells to form fifos, or be initialized via serial eeprom on power-up and used as roms. the ql5332 device meets pci 2.2 electrical and timing specifications and has been fully hardware- tested. this device also supports the win'98 and pc'98 standards. the ql5332 device features 3.3- volt operation with multi-volt compatible i/os. thus it can easily operate in 3-volt systems and is fully compatible with 3.3v, 5v or universal pci card applications. the pci controller is a 32-bit/33 mhz pci 2.2 com- pliant master/target controller. it is capable of infi- nite length master write and read transactions at zero wait states (132 mbytes/second). the master will never insert wait states during transfers, so data should be supplied or received by fifos, which can be config- ured in the programmable region of the device. the master is capable of initiating any type of pci com- mand, including configuration cycles and memory write and invalidate (mwi). this enables the ql5332 device to act as a pci host. the master controller will most often be operated by a dma controller in the programmable region of the device. a dma control- ler reference design is available. the target interface offers full pci configuration space and flexible target addressing. it supports zero- wait-state target write and one-wait-state target read operations. it also supports retry, disconnect with/ without data transfer, and target abort requested by the backend. any number of 32-bit bars may be con- figured, as either memory or i/o space. all required and optional pci 2.2 configuration space registers can be implemented within the programmable region of the device. a reference design of a target configu- ration and addressing module is provided. the interface ports are divided into a set of ports for master transactions and a set for target transactions. the master dma controller and target configuration space and address decoding are done in the pro- grammable logic region of the device. since these functions are not timing critical, leaving these ele- ments in the programmable region allows the greatest degree of flexibility to the designer. reference dma controller, configuration space, and address decod- ing blocks are included so that the design cycle can be minimized. the configuration space is completely customizable in the programmable region of the device. pci address and command decoding is performed by logic in the programmable section of the device. this allows support for any size of memory or i/o space for back-end logic. it also allows the user to implement any subset of the pci commands supported by the ql5332. quicklogic provides a reference address register/counter and command decode block. architecture overview pci controller configuration space and address decode
3 ql5332 - quickpci tm the customizable dma controller included with the quickworks design software contains the following features: configurable dma count size for reads and writes (up to 30-bits) configurable dma burst size for pci (including unlimited/continuous burst) customizable pci command to use by core customizable byte enable signal programmable arbitration between dma read & write transactions dma registers may be mapped to any area of target memory space - read address (32-bit register) - write address (32-bit register) - read length (16-bit register) / write length (16-bit register) - control and status (32-bit register, includes 8 bit burst length) dma registers are available to the local design or the pci bus programmable interrupt control to signal end of transfer or other event fifos may be created with the ram/fifo wizard in the quickworks tools. the figure below shows the graphical interface used to create these fifos. fifos may be designed up to 256 deep. with 12 ram cells available in the ql5332, that allows for up to 6 fifos at 64 deep (36 wide), 3 fifos at 128 deep (36 wide), or 1 fifo at 256 deep (48 wide). figure 2: graphical interface to create fifo dma master/target control configurable fifos
4 preliminary ql5332 - quickpci tm 4 the figure below shows the interface symbol you would use in your schematic design in order to attach the local interface programmable logic design to the pci core. if you were designing with a top-level verilog or vhdl file, then you would use a structural instantiation of this pci32n block, instead of a graphical symbol. figure 3: pci interface symbol pci interface symbol
5 ql5332 - quickpci tm the internal signals used to interface with the pci controller in the ql5332 are listed below, along with a description of each signal. the direction of the signal indicates if it is an input provided by the local interface (i) or an output pro- vided by the pci controller (o). signals that end with the character ?n? should be considered active-low (for example, mst_irdyn ). pci_cmd[3:0] i pci command to be used for the master transaction. this signal must remain unchanged throughout the period when mst_burst_req is active. pci commands considered as reads include interrupt acknowledge, i/o read, memory read, configuration read, memory read multiple, memory read line. pci commands considered as writes include special cycle, i/o write, memory write, configuration write, memory write and invalidate. users should make sure that only valid pci commands are supplied. mst_burst_req i request use of the pci bus. when it is active, the core requests the pci bus and then generates a master trans- action. this signal should be held active until all requested data are transferred on the pci bus and deactivated in the 2nd clock cycle following the last data transfer on pci (to avoid being considered as requesting a new transaction). mst_wrad[31:0] i address for master dma writes. this address must be treated as valid from the beginning of a dma write until the dma write operation is complete. it should be incremented (by 4 bytes) each time data is transferred on the pci bus. mst_rdad[31:0] i address for master dma reads. this address must be treated as valid from the beginning of a dma read until the dma read operation is complete. it should be incremented (by 4 bytes) each time data is transferred on the pci bus. mst_wrdata[31:0] i data for master dma writes (to pci bus). mst_be[3:0] i byte enables for master dma reads and writes. active-low. mst_wrdata_valid i data and byte enable valid on mst_wrdata[31:0] (for master write only) and mst_be[3:0] (for both master read and write). mst_wrdata_rdy o data receive acknowledge for mst_wrdata[31:0] (for master write only) and mst_be[3:0] (for both). this serves as the push control for the internal fifo and the pop control for the external fifo (in fpga region) which provides data and byte enables to the pci32 core. mst_be_sel i byte enable select for master transactions. when low, mst_be[3:0] should remain constant throughout the entire transfer (when mst_burst_req is active) and it is used for every data phase of the master transaction. when high, mst_be[3:0] pushed into internal fifo (along with data in case of master write) is used. should be held constant throughout the transaction. mst_wrburst_done o master write transaction is completed. active for only one clock cycle. mst_rd_term_sel i master read termination mode select when mst_be_sel is high. when both mst_be_sel and mst_rd_term_sel are high, master read termination happens when the internal fifo is empty, and mst_two_reads and mst_one_read are ignored. when either signal is low, mst_two_reads and mst_one_read are used to signal end of master read. should be held constant throughout the transaction. mst_one_read i this signals to the pci32 core that only one data transfer remains to be read in the burst read. mst_two_reads i two data transfers remain to be read in the burst read. it is not used for single-data-phase master read transactions. mst_rddata_valid o master read data valid on usr_addr_wrdata[31:0]. this serves as the push control for the external fifo (in fpga region) that receives data from the pci32 core. mst_rdburst_done o master read transaction is completed. active for only one clock cycle. flush_fifo i internal fifo flush. fifo flushed immediately after it is active (synchronized with pci clock). mst_latcnten i enable latency counter. set to 0 to ignore the latency timer in the pci configuration space (offset 0ch). for full pci compliance, this port should be always set to 1. mst_xfer_d1 o data was transferred on the previous pci clock. useful for updating dma transfer counts on dma read operations. mst_last_cycle o active during the last data transfer of a master transaction. mst_reqn o copy of the pci reqn signal generated by ql5x33 as pci master. not usually used in the back-end design. pci master interface
6 preliminary ql5332 - quickpci tm 6 mst_irdyn o copy of the pci irdyn signal generated by ql5x33 as pci master. valid only when ql5x33 is the pci mas- ter. kept low otherwise. not usually used in the back-end design. mst_tabort_det o target abort detected during master transaction. this is normally an error condition to be handled in the dma controller. mst_tto_det o target timeout detected (no response from target). this is normally an error condition to be handled in the dma controller. usr_addr_wrdata[31:0] o target address, and target write data. during all target accesses, the address is presented on usr_addr_wrdata[31:0] at the same time usr_adr_valid is active. during target write transactions, this port also presents valid write data to the pci configuration space or user logic when usr_adr_inc is active. usr_cbe[3:0] o pci command and byte enables. during target accesses, the pci command is presented on usr_cbe[3:0] at the same time usr_adr_valid is active. this port also presents active-low byte enables to the pci con- figuration space or user logic. usr_adr_valid o indicates the beginning of a pci transaction, and that a target address is valid on usr_addr_wrdata[31:0] and the pci command is valid on usr_cbe[3:0]. when this signal is active, the target address must be latched and decoded to determine if this address belongs to the device's memory or i/o space. also, the pci command must be decoded to determine the type of pci transaction. on subsequent clocks of a tar- get access, this signal is low, indicating that address is not present on usr_addr_wrdata[31:0]. usr_adr_inc o indicates that the target address should be incremented, because the previous data transfer has com- pleted. during burst target accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when usr_adr_valid is active), and must therefore be latched and incre- mented (by 4) for subsequent data transfers. note that during target write transactions, usr_adr_inc indi- cates valid data on usr_addr_wrdata[31:0] that must be accepted by the backend logic (regardless of the state of usr_rdy). during read transactions, usr_adr_inc signals to the backend that the pci core has presented the read data on the pci bus (trdyn asserted). usr_rddecode i this signal should be the combinatorial decode of the "user read" command from usr_cbe[3:0]. this command may be mapped from any of the pci "read" commands, such as memory read, memory read line, memory read multiple, i/o read, etc. it is internally gated with usr_adr_valid. usr_wrdecode i this signal should be the combinatorial decode of the "user write" command from usr_cbe[3:0]. this command may be mapped from any of the pci "write" commands, such as memory write or i/o write. it is internally gated with usr_adr_valid. usr_select i this signal should be driven active when the address on usr_addr_wrdata[31:0] has been decoded and determined to be within the address space of the device. usr_addr_wrdata[31:0] must be compared to each of the valid base address registers in the pci configuration space. also, this signal must be gated by the memory access enable or i/o access enable registers in the pci configuration space (command register bits 1 or 0 at offset 04h). internally gated with usr_adr_valid. usr_write o this signal is active throughout a "user write" transaction, which has been decoded by usr_wrdecode at the beginning of the transaction. the write strobe for individual dwords of data (on usr_addr_wrdata[31:0]) during a user write transaction should be generated by logically anding this sig- nal with usr_adr_inc. cfg_write o this signal is active throughout a "configuration write" transaction. the write strobe for individual dwords of data (on usr_addr_wrdata[31:0]) during a configuration write transaction should be gener- ated by logically anding this signal with usr_adr_inc. usr_read o this signal is active throughout a "user read" transaction, which has been decoded by usr_rddecode at the beginning of the transaction. cfg_read o this signal is active throughout a "configuration read" transaction. cfg_rddata[31:0] i data from the pci configuration registers, required to be presented during pci configuration reads. usr_rddata[31:0] i data from the back-end user logic, required to be presented during pci user reads. pci target interface
7 ql5332 - quickpci tm cfg_cmdreg3 i bits 3 from the command register in the pci configuration space (offset 04h). enable special cycle monitoring. if high, the core reports data parity error in special cycles through serrn if cfg_cmdreg8 is active. cfg_cmdreg4 i bits 4 from the command register in the pci configuration space (offset 04h). memory write and invali- date (mwi) enable. if high, the core generates mwi transactions as requested by the backend. otherwise it uses memory write instead even if mwi is requested. cfg_cmdreg6 i bits 6 from the command register in the pci configuration space (offset 04h). parity error response. if high, the core uses perrn to report data parity errors. otherwise it never drives it. cfg_cmdreg8 i bits 8 from the command register in the pci configuration space (offset 04h). serrn enable. if high, the cores uses serrn to report address parity errors if cfg_cmdreg6 is high. cfg_latcnt[7:0] i 8-bit value of the latency timer in the pci configuration space (offset 0ch). usr_mstrdad_sel i used when a target read operation should return the value set on the mst_rdad[31:0] pins. this select pin saves on logic which would otherwise need to be used to multiplex mst_rdad[31:0] into the usr_rddata[31:0] bus. when this signal is asserted, the data on usr_rddata[31:0] is ignored. usr_mstwrad_sel i used when a target read operation should return the value set on the mst_wrad[31:0] pins. this select pin saves on logic which would otherwise need to be used to multiplex mst_wrad[31:0] into the usr_rddata[31:0] bus. when this signal is asserted, the data on usr_rddata[31:0] is ignored. cfg_perr_det o parity error detected on the pci bus. when this signal is active, bit 15 of the status register must be set in the pci configuration space (offset 04h). cfg_serr_sig o system error asserted on the pci bus. when this signal is active, the signalled system error bit, bit 14 of the status register, must be set in the pci configuration space (offset 04h). cfg_mstperr_det o data parity error detected on the pci bus by the master. when this signal is active, bit 8 of the status reg- ister must be set in the pci configuration space (offset 04h). usr_trdy o inverted copy of the trdyn signal as driven by the pci target interface. valid only within a target access. usr_stopo o inverted copy of the stopn signal as driven by the pci target interface. valid only within a target access. usr_devsel o inverted copy of the devseln signal as driven by the pci target interface. valid only within a target access. usr_last_cycle_d1 o active one clock cycle after the last data phase (may not with data transfer) occurs on pci and inactive one clock cycle afterwards. usr_rdy i used to delay (add wait states to) a target pci transaction when the backend needs additional time to pro- vide data (read) or accept data (write). subject to pci latency restrictions. usr_stop i used to prematurely stop a pci target access on the next pci clock. usr_abort i used to signal target abort on pci when the backend has fatal error and is unable to complete a transac- tion. rarely used. usr_interrupt i used to signal an interrupt on the pci bus pci internal signals pci_clock o pci clock. pci_reset o pci reset signal. pci_irdyn_d1 o copy of the irdyn signal from the pci bus, delayed by one clock. pci_framen_d1 o copy of the framen signal from the pci bus, delayed by one clock. pci_devseln_d1 o copy of the devseln signal from the pci bus, delayed by one clock. pci_trdyn_d1 o copy of the trdyn signal from the pci bus, delayed by one clock. pci_stopn_d1 o copy of the stopn signal from the pci bus, delayed by one clock. pci_idsel_d1 o copy of the idsel signal from the pci bus, delayed by one clock.
8 preliminary ql5332 - quickpci tm 8 the ql5332 device has twelve 1,152-bit ram mod- ules, for a total of 13,824 ram bits. using two ?mode? pins, designers can configure each module into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 blocks. see the figure below. the blocks are also easily cascadable to increase their effective width or depth. the ram modules are ?dual-ported?, with com- pletely independent read and write ports and separate read and write clocks. the read ports support asynchronous and synchronous operation, while the write ports support synchronous opera- tion. each port has 18 data lines and 9 address lines, allowing word lengths of up to 18 bits and address spaces of up to 512 words. depending on the mode selected, however, some higher order data or address lines may not be used. the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read opera- tion (asyncrd input low), or as a flow-through enable for asynchronous read operation (asyn- crd input high). designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. this approach allows up to 512-deep configurations as large as 24 bits wide in the ql5332 device. a similar technique can be used to create depths greater than 512 words. in this case address signals higher than the eighth bit are encoded onto the write enable (we) input for write operations. the read data outputs are multiplexed together using encoded higher read address bits for the multiplexer select signals. figure 4: ram module jtag pins support ieee standard 1149.1a to provide boundary scan capability for the ql5332 device. six pins are dedicated to jtag and programming functions on each ql5332 device, and are unavailable for general design input and output signals. tdi, tdo, tck, tms, and trstb are jtag pins. a sixth pin, stm, is used only for programming. ram module features address buses [a:0] data buses [w:0] 64x18 [5:0] [17:0] 128x9 [6:0] [8:0] 256x4 [7:0] [3:0] 512x2 [8:0] [1:0] mode[1:0] wa[a:0] wd[w:0] we wclk ram module asyncrd ra[a:0] rd[w:0] re rclk jtag support jtag support
9 ql5332 - quickpci tm software support for the ql5332 device is available through the quick works ? development package. this turnkey pc-based quick works ? package, shown in figure 5, provides a complete esp software solution with design entry, logic synthesis, place and route, and simulation. quick works ? includes vhdl, verilog, schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the integrated synplicity synplify lite ? tool, specially tuned to take advantage of the ql5332 architecture. quick works also provides functional and timing simulation for guaranteed timing and source-level debugging. the unix-based quick tools ? package is a subset of quick works ? and provides a solution for designers who use schematic-only design flow third-party tools for design entry, synthesis, or simulation. quick tools ? reads edif netlists and provides support for all quicklogic devices. quick tools ? also supports a wide range of third-party modeling and simulation tools. figure 5: quickworks ? tool suite development tool support schematic schematic turbo hdl editor third party design entry & synthesis third party simulation vhdl/ vhdl/ verilog verilog scs tools silos iii simulator optimize, place, route mixed-mode design mixed-mode design synplify-lite hdl synthesis quick works design software a ldec
10 preliminary ql5332 - quickpci tm 10 absolute maximum ratings vcc voltage . . . . . . . . . . . . . . . . -0.5 to 4.6v vccio voltage . . . . . . . . . . . . . . -0.5 to 7.0v input voltage . . . . . . . . -0.5v to vccio +0.5v latch-up immunity . . . . . . . . . . . . 200ma dc input current . . . . . . . . . . . . 20 ma esd pad protection . . . . . . . . . . . 2000v storage temperature . . . . . .-65 o c to + 150 o c lead temperature . . . . . . . . . . . . . . . . 300 o c operating range dc characteristics notes: [1] capacitance is sample tested only. [2] only one output at a time. duration should not exceed 30 seconds. [3] for -a commercial grade device only. maximum icc is 3 ma for all industrial grade devices. for ac conditions, contact quicklogic customer engineering. electrical specifications symbol parameter industrial commercial unit min max min max vcc supply voltage 3.0 3.6 3.0 3.6 v vccio i/o input tolerance voltage 3.0 5.5 3.0 5.25 v ta ambient temperature -40 85 0 70 c k delay factor -a speed grade 0.43 0.95 0.46 0.93 symbol parameter conditions min max unit vih input high voltage 0.5vcc vccio+0.5 v vil input low voltage -0.5 0.3vcc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9vcc v vol output low voltage iol = 16 ma 0.45 v iol = 1.5 ma 0.1vcc v ii i or i/o input leakage current vi = vccio or gnd -10 10 a ioz 3-state out p ut leaka g e current vi = vccio or gnd -10 10 a ci input capacitance [1] 10 pf ios output short circuit current [2] vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current [3] vi , vio = vccio or gnd 0.50 ( t yp) 2ma iccio d.c. supply current on vccio 0 100 a
11 ql5332 - quickpci tm ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the ?operating range? section by the following numbers.) logic cells ram cell synchronous write timing notes: [4] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [5] these limits are derived from a representative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analy- sis of your particular design. symbol parameter propagation delays (ns) fanout [4] 12348 tpd combinatorial delay [5] 1.4 1.7 2.0 2.3 3.5 tsu setup time [5] 1.8 1.8 1.8 1.8 1.8 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.8 1.1 1.4 1.7 2.9 tcwhi clock high time 1.6 1.6 1.6 1.6 1.6 tcwlo clock low time 1.6 1.6 1.6 1.6 1.6 tset set delay 1.4 1.7 2.0 2.3 3.5 treset reset delay 1.2 1.5 1.8 2.1 3.3 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) fanout [4] 12348 tswa wa setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwa wa hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswd wd setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwd wd hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswe we setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwe we hold time to wclk 0.0 0.0 0.0 0.0 0.0 twcrd wclk to rd (wa=ra) [4] 5.0 5.3 5.6 5.9 7.1
12 preliminary ql5332 - quickpci tm 12 ram cell synchronous read timing ram cell asynchronous read timing input-only cells clock cells notes: [6] the array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 8 loads per half column. the global clock has up to 11 loads per half column. symbol parameter propagation delays (ns) fanout 12348 tsra ra setup time to rclk 1.0 1.0 1.0 1.0 1.0 thra ra hold time to rclk 0.0 0.0 0.0 0.0 0.0 tsre re setup time to rclk 1.0 1.0 1.0 1.0 1.0 thre re hold time to rclk 0.0 0.0 0.0 0.0 0.0 trcrd rclk to rd [5] 4.0 4.3 4.6 4.9 6.1 symbol parameter propagation delays (ns) fanout 12348 rpdrd ra to rd [5] 3.0 3.3 3.6 3.9 5.1 symbol parameter propagation delays (ns) fanout [5] 123481224 tin high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlesu input register clock enable setup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 propagation delays (ns) loads per half column [6] symbols parameter 12 3 48 101215 tack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 1.8 tgckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tgckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 1.4
13 ql5332 - quickpci tm i/o cell input delays i/o cell output delays notes: [7] the following loads are used for tpxz: symbol parameter propagation delays (ns) fanout [5] 1234810 ti/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 tlorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.1 2.5 3.1 3.6 4.7 touthl output delay high to low 2.2 2.6 3.2 3.7 4.8 tpzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 tpzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 tphz output delay high to tri-state [8] 2.0 tplz output delay low to tri-state [8] 1.2 5 pf 1k ? 5 pf 1k ? tphz tplz
14 preliminary ql5332 - quickpci tm 14 the ql5332 device pins are indicated in the table below. these are pins on the device, some of which connect to the pci bus, and others that are programmable as user io. * see quicknote 65 on the quicklogic web site for information on ram initialization. pin type descriptions type description in input. a standard input-only signal out totem pole output. a standard active out- put driver t/s tri-state. a bi-directional, tri-state input/ output pin s/t/s sustained tri-state. an active low tri-state signal driven by one pci agent at a time. it must be driven high for at least one clock before being disabled (set to hi-z). a pull- up needs to be provided by the pci system central resource to sustain the inactive state once the active driver has released the sig- nal. o/d open drain. allows multiple devices to share this pin as a wired-or. pin/bus name type function vcc in supply pin. tie to 3.3v supply. vccio in supply pin for i/o. set to 3.3v for 3.3v i/o, 5v for 5.0v compliant i/o gnd in ground pin. tie to gnd on the pcb. i/o t/s programmable input/output/tri-state/bi- directional pin. glck/i in programmable global network or input- only pin. tie to vcc or gnd if unused. aclk/i in programmable array network or input- only pin. tie to vcc or gnd if unused. tdi/rsi* in jtag data in/ram init. serial data in. tie to vcc if unused. connect to serial eprom data for ram init. tdo/rco* out jtag data out/ram init clock. leave unconnected if unused. connect to serial eprom clock for ram init. tck in jtag clock. tie to gnd if unused. tms in jtag test mode select. tie to vcc if unused. trstb/rro* in jtag reset/ram init. reset out. tie to gnd if unused. connect to serial eprom reset for ram init. stm in quicklogic reserved pin. tie to gnd on the pcb.
15 ql5332 - quickpci tm pin/bus name type function ad[31:0] t/s pci address and data: 32 bit multiplexed address/data bus. cben[3:0] t/s pci bus command and byte enables: multiplexed bus which contains byte enables for ad[31:0] or the bus command during the address phase of a pci transaction. par t/s pci parity: even parity across ad[31:0] and c/ben[3:0] busses. driven one clock after address or data phases. master drives par on address cycles and pci writes. the target drives par on pci reads. framen s/t/s pci cycle frame: driven active by current pci master during a pci transac- tion. driven low to indicate the address cycle, driven high at the end of the transaction. devseln s/t/s pci device select. driven by a target that has decoded a valid base address. clk in pci system clock input. rstn in pci system reset input reqn t/s pci request. indicates to the arbiter that this pci agent (initiator) wishes to use the bus. a point to point signal between the pci device and the system arbiter. gntn in pci grant. indicates to a pci agent (initiator) that it has been granted access to the pci bus by the arbiter. a point to point signal between the pci device and the system arbiter. perrn s/t/s pci data parity error. driven active by the initiator or target two clock cycles after a data parity error is detected on the ad and c/be# busses. serrn o/d pci system error: driven active when an address cycle parity error, data par- ity error during a special cycle, or other catastrophic error is detected. idsel in pci initialization device select. use to select a specific pci agent during system initialization. irdyn s/t/s pci initiator ready. indicates the initiator?s ability to complete a read or write transaction. data transfer occurs only on clock cycles where both irdyn and trdyn are active. trdyn s/t/s pci target ready. indicates the target?s ability to complete a read or write transaction. data transfer occurs only on clock cycles where both irdyn and trdyn are active. stopn s/t/s pci stop. used by a pci target to end a burst transaction. intan o/d interrupt a. asynchronous active-low interrupt request. ql5332 external device pins
16 preliminary ql5332 - quickpci tm 16 figure 6: 208-pin pqfp figure 7: 256-pin pbga pinout diagrams QL5332-33APQ208C quickpci pin #1 pin #53 pin #157 pin #105 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w bottom view pin #a1 corner
17 ql5332 - quickpci tm ql5332 - 208 pqfp pinout table pq208 function pq208 function pq208 function pq208 function pq208 function 1 i/o 43 gnd 85 ad[3] 127 gnd 169 i/o 2 i/o 44 idsel 86 ad[2] 128 i/o 170 i/o 3 i/o 45 ad[23] 87 ad[1] 129 gclk/i 171 i/o 4 i/o 46 ad[22] 88 ad[0] 130 aclk/i 172 i/o 5 i/o 47 ad[21] 89 i/o 131 vcc 173 i/o 6 i/o 48 ad[20] 90 i/o 132 gclk/i 174 i/o 7 i/o 49 ad[19] 91 i/o 133 gclk/i 175 i/o 8 i/o 50 ad[18] 92 i/o 134 vcc 176 i/o 9 i/o 51 ad[17] 93 i/o 135 i/o 177 gnd 10 vcc 52 ad[16] 94 i/o 136 i/o 178 i/o 11 i/o 53 cben[2] 95 gnd 137 i/o 179 i/o 12 gnd 54 tdi 96 i/o 138 i/o 180 i/o 13 i/o 55 framen 97 vcc 139 i/o 181 i/o 14 i/o 56 irdyn 98 i/o 140 i/o 182 gnd 15 i/o 57 trdyn 99 i/o 141 i/o 183 i/o 16 i/o 58 devseln 100 i/o 142 i/o 184 i/o 17 i/o 59 gnd 101 i/o 143 i/o 185 i/o 18 i/o 60 stopn 102 i/o 144 i/o 186 i/o 19 i/o 61 vcc 103 trstb 145 vcc 187 vccio 20 i/o 62 i/o 104 tms 146 i/o 188 i/o 21 i/o 63 i/o 105 i/o 147 gnd 189 i/o 22 i/o 64 perrn 106 i/o 148 i/o 190 i/o 23 gnd 65 i/o 107 i/o 149 i/o 191 i/o 24 intan 66 serrn 108 i/o 150 i/o 192 i/o 25 rstn 67 par 109 i/o 151 i/o 193 i/o 26 aclk/i 68 cben[1] 110 i/o 152 i/o 194 i/o 27 vcc 69 ad[15] 111 i/o 153 i/o 195 i/o 28 gclk/i 70 ad[14] 112 i/o 154 i/o 196 i/o 29 clk 71 ad[13] 113 i/o 155 i/o 197 i/o 30 vcc 72 ad[12] 114 vcc 156 i/o 198 i/o 31 gntn 73 gnd 115 i/o 157 tck 199 gnd 32 reqn 74 ad[11] 116 gnd 158 stm 200 i/o 33 ad[31] 75 ad[10] 117 i/o 159 i/o 201 vcc 34 ad[30] 76 ad[9] 118 i/o 160 i/o 202 i/o 35 ad[29] 77 ad[8] 119 i/o 161 i/o 203 i/o 36 ad[28] 78 gnd 120 i/o 162 i/o 204 i/o 37 ad[27] 79 cben[0] 121 i/o 163 gnd 205 i/o 38 ad[26] 80 ad[7] 122 i/o 164 i/o 206 i/o 39 ad[25] 81 ad[6] 123 i/o 165 vcc 207 tdo 40 ad[24] 82 ad[5] 124 i/o 166 i/o 208 i/o 41 vcc 83 vccio 125 i/o 167 i/o 42 cben[3] 84 ad[4] 126 i/o 168 i/o
18 preliminary ql5332 - quickpci tm 18 ql5332 - 256 pbga pinout table pb256 function pb256 function pb256 function pb256 function pb256 function pb256 function a1 gnd c4 i/o e19 i/o l2 aclk/i t17 i/o v20 i/o a2 i/o c5 i/o e20 i/o l3 rstn t18 i/o w1 i/o a3 i/o c6 i/o f1 i/o l4 gclk/i t19 nc w2 i/o a4 i/o c7 i/o f2 i/o l17 vcc t20 i/o w3 tdi a5 i/o c8 i/o f3 i/o l18 i/o u1 i/o w4 gntn a6 i/o c9 vccio f4 vcc l19 i/o u2 i/o w5 ad[27] a7 i/o c10 i/o f17 vcc l20 i/o u3 i/o w6 cben[3] a8 i/o c11 i/o f18 nc m1 i/o u4 gnd w7 ad[21] a9 i/o c12 i/o f19 i/o m2 i/o u5 ad[26] w8 ad[20] a10 i/o c13 i/o f20 i/o m3 i/o u6 vcc w9 cben[2] a11 i/o c14 i/o g1 i/o m4 nc u7 ad[22] w10 devseln a12 i/o c15 i/o g2 nc m17 nc u8 gnd w11 perrn a13 i/o c16 i/o g3 i/o m18 i/o u9 framen w12 cben[1] a14 i/o c17 i/o g4 i/o m19 i/o u10 vcc w13 par a15 i/o c18 i/o g17 i/o m20 i/o u11 i/o w14 ad[10] a16 i/o c19 i/o g18 i/o n1 i/o u12 i/o w15 ad[9] a17 i/o c20 i/o g19 nc n2 i/o u13 gnd w16 ad[5] a18 i/o d1 i/o g20 i/o n3 i/o u14 ad[11] w17 ad[1] a19 tck d2 i/o h1 i/o n4 gnd u15 vcc w18 ad[0] a20 i/o d3 i/o h2 i/o n17 gnd u16 ad[4] w19 i/o b1 tdo d4 gnd h3 i/o n18 i/o u17 gnd w20 trstb b2 i/o d5 i/o h4 gnd n19 i/o u18 i/o y1 intan b3 i/o d6 vcc h17 gnd n20 i/o u19 i/o y2 nc b4 i/o d7 i/o h18 i/o p1 i/o u20 i/o y3 reqn b5 i/o d8gndh19i/o p2 i/o v1 i/o y4ad[31] b6 i/o d9 i/o h20 i/o p3 i/o v2 nc y5 ad[29] b7 i/o d10 i/o j1 i/o p4 i/o v3 i/o y6 ad[25] b8 i/o d11 vcc j2 i/o p17 i/o v4 ad[30] y7 ad[23] b9 i/o d12 i/o j3 nc p18 i/o v5 ad[28] y8 ad[19] b10 i/o d13 gnd j4 i/o p19 nc v6 ad[24] y9 ad[17] b11 i/o d14 i/o j17 nc p20 i/o v7 idsel y10 irdyn b12 i/o d15 vcc j18 i/o r1 nc v8 ad[18] y11 i/o b13 i/o d16 i/o j19 i/o r2 i/o v9 ad[16] y12 serrn b14 i/o d17 gnd j20 gclk / i r3 i/o v10 trdyn y13 ad[14] b15 i/o d18 i/o k1 i/o r4 vcc v11 stopn y14 ad[12] b16 i/o d19 i/o k2 i/o r17 vcc v12 vccio y15 ad[8] b17 nc d20 i/o k3 i/o r18 i/o v13 ad[15] y16 ad[7] b18 stm e1 nc k4 vcc r19 i/o v14 ad[13] y17 ad[3] b19 nc e2 i/o k17 gclk/i r20 i/o v15 cben[0] y18 i/o b20 i/o e3 i/o k18 aclk/i t1 nc v16 ad[6] y19 i/o c1 i/o e4 i/o k19 gclk/i t2 i/o v17 ad[2] y20 nc c2 i/o e17 i/o k20 nc t3 i/o v18 i/o c3 i/o e18 i/o l1 clk t4 nc v19 tms

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